This invention relates to hot charge-carrier transistors having a base region through which current flow is by hot majority charge-carriers, and relates particularly but not exclusively to hot electron transistors formed with monocrystalline gallium arsenide and suitable for operation at room temperature.
Published United Kingdom patent application No. 2 056 166 discloses hot charge-carrier transistors comprising a base region through which current flow is by hot charge-carriers of one conductivity type. Barrier-forming means forms a base-collector barrier with said base region. An emitter-base barrier region which is doped with impurity of the opposite conductivity type is sufficiently thin as to form with a part of the base region of said one conductivity type a bulk unipolar diode for injection of the hot charge-carriers of said one conductivity type into the base region during operation of the transistor. These transistors are suitable for operation at room temperature.
In the transistors described in GB Pat. No. 2 056 166, the emitter-base barrier region is undepleted over a part of its thickness by the depletion layer or layers present at the emitter-base barrier at zero bias. The application of a minimum bias voltage is necessary to establish (by avalanche breakdown, inter-band tunnelling or depletion-layer punch-through) a supply of hot majority charge-carriers having energies above the base-collector barrier; this improves the collection efficiency of the transistor as described in GB Pat. No. 2 056 166. The present invention may be incorporated in transistors having such an emitter-base barrier region, but it may also be incorporated in transistors in which the doped emitter-base barrier region is substantially depleted across the whole of its thickness at zero bias, for example as described in U.S. Pat. No. 4149174.
Several particular examples of these transistors are described in GB Pat. No. 2 056 166. In the hot electron device structures of FIGS. 3 and 4, there are possible sources of free minority carriers (holes), for example the undepleted p type part of the barrier region 4, an undepleted p type guard ring 11, and electron-hole pair generation in the case of avalanche breakdown of the barrier region 4. There are circumstances in which these free minority carriers in the transistor structure may be trapped by the emitter-base barrier region 4 during operation of the transistor, and such minority carrier storage in the emitter-base barrier region 4 may reduce the barrier height, increase the capacitance and reduce the speed of the transistor.
In the FIG. 3 device structure in GB Pat. No. 2 056 166 both the base region 2 and emitter-base barrier region 4 are formed by ion implantation and extend to the top major surface of a silicon device body where the base region 2 is contacted by the base contact 8 at an area adjoining the p type guard ring 11. In the FIG. 7 device structure, both the base region 2 and the emitter-base barrier region 4 are formed by molecular beam epitaxy of appropriately-doped gallium arsenide, and the gallium arsenide barrier region 4 is removed from the area where the base contact 8 is to be provided. Although the gallium arsenide base region 2 has a very high opposite conductivity type doping compared to those of the emitter-base and base-collector barrier regions 4 and 1, much care is needed to ensure that the etching process is terminated after the region 4 is removed but before the region 1 is reached.